A two phase clock generation circuit is a device that generates both true and complement clock signals at an output thereof. Such devices are used today in a variety of complementary metal oxide semiconductor (CMOS) based designs. Ideally, the rising edge of the true clock signal will align in time with the falling edge of the complement clock signal, and vice versa. However, in past two phase clock designs, the alignment between the two clock signals is optimal for only a predetermined set of ideal conditions. If these conditions are varied, undesired phase offsets begin to occur between the true and complement clock signals that reduce the overall effectiveness and quality of the signals. For example, variations in process, operating voltage, and operating temperature can introduce significant offsets between the true and complement clock signals that can compromise system performance. With chip speeds continually rising, it is becoming increasingly important that phase offsets between the true and complement clock signals be kept to a minimum for a wide range of possible process and operating conditions.
Therefore, there is need for a two phase clock generation circuit that is less sensitive to variations in process and operating conditions.